Physical Design for Reduced Delay Uncertainty in High Performance Clock Distribution Networks

Controlling the clock signal delay in the presence of various noise sources, process parameter variations, and environmental effects represents a fundamental problem in the design of high speed synchronous circuits. A methodology for enhancing the layout of the clock tree to reduce the uncertainty of the clock signal is presented in this paper. The primary objective of the proposed methodology is to satisfy the timing constraints of the most critical data paths in a circuit. Two different design approaches are described to reduce the delay uncertainty of the clock signal. The first approach determines the size of the clock buffers to reduce variations in the clock delay. The second approach exploits the common portion among the clock paths that drive the registers of the most critical data paths. The application of these techniques to a set of benchmark circuits demonstrates some interesting tradeoffs among the aggregate clock buffer size, the total wire length of the clock tree, and the power dissipation.